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asxeem/openaliro
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From a clean checkout to a phone unlocking the door. Pick a track; it opens in place.
Pick a track
HardwareBoards, wiring, and the UWB radio⌄
- nRF5340 bring-upThe primary target: DK + shields, first flash, and what a healthy boot looks like.
- ESP32-S3 wiring checklistDWM3000EVB to ESP32-S3, pin by pin — the table CI keeps in sync with
board_pins.h. - Flash an ESP32 lock from the browserNo toolchain: this site writes the merged firmware image (ESP32-S3 or ESP32-C5) over WebSerial (Chrome, Edge, or Firefox).
- Hardware validation checklistWhat to prove on the bench that automated CI cannot.
Supported targets
Primary: nRF5340 DK + DWM3000EVB shield (validated, measured).
Port: ESP32-S3 with the same DWM3000EVB (ports/esp32).
Software & toolchainEverything to install, per target⌄
nRF5340 — the primary target
$git clone https://github.com/asxeem/openaliro.git
$cd openaliro
$nrfutil sdk-manager toolchain install --ncs-version v3.3.0
$make bootstrap
The first command runs once per machine; bootstrap pulls ~6.5 GB into ./workspace.
Docs tooling
$brew install doxygen graphviz
$make docs
The site lands in ./site.
The five-step version of this track sits on the landing page.
Build, flash & testThe make targets that drive everything⌄
$make build
$make flash-erase
$make test
$make coverage
Images land in ./build/merged.hex; first flash needs the erase; tests run on the host, no hardware.
Firmware internalsHow the reader is put together⌄
Protocol & researchHow the unlock actually works on air⌄
Project & contributingCI, releasing, and where the work happens⌄
- RepositorySource, issues and pull requests on GitHub.
- IssuesReport a bug or pick something up.
- ReleasingHow a release is cut and what gates it.
- Porting openaliroWhat moving the engine to a new chipset costs, and how to prove it.
What CI checks on every push
Host tests with a coverage floor, ASan/UBSan sanitizer runs, clang-format and clang-tidy, shell and workflow lint, fuzzing, CBMC proofs, port tests, firmware image builds for both targets, and a patch-drift gate that keeps the ports honest.